Abstract:

A pulse shielded SRAM cell is proposed for increasing the SEU performance which is used in block RAM (BRAM) and configuration memory of FPGAs. The pulse current from an incident particle is shielded because of the increasing single event response time for a SRAM cell. The SEU performance is verified by the 64k SRAMs with SEU threshold improving from 25 MeV·cm 2·mg -1 to 45 MeV·cm 2·mg -1 at only 21.3% additional cost of the SRAM cell area. By adopting the pulse shielded SRAM cell and radiation hardened process, the 300,000-gate FPGA possesses radiation features: SEU threshold higher than 37.3 MeV·cm 2·mg -1 ; SEL threshold higher than 99.8 MeV·cm 2·mg -1 and total dose tolerance higher than 200 krad(Si) respectively.

Key words:  FPGA, SRAM cell, SOI process, Radiation hardened, SEU